As feature size in integrated circuits decreases, it is increasingly important to reduce the resistance-capacitance delay (RC delay) attributable to interconnects used in such circuits. In order to reduce this RC delay, it is currently thought that advanced interconnects should have a reduced dielectric constant (k). In particular, these interconnects should be made of low-k materials. As a first step, carbonated silicon dioxide (SiOC) films have been conventionally introduced in the 90-120 nm technology nodes. A current focus is to further improve the k-value by introducing pores in such carbonated silicon dioxide films.
The term “carbonated silicon dioxide films” and the corresponding formula “SiOC” are used to designate silicon dioxide films including carbon therein (e.g., by using CH3SiH3 in place of the SiH4 that is often used as a precursor in the formation of a silicon dioxide layer). Such films are sometimes also referred to in the art as carbon-doped silicon dioxide films.
Carbonated silicon dioxide films are being developed by several vendors, using chemical vapor deposition or spin-on coating techniques. Several vendors are currently developing CVD-deposited SiOC films using a “porogen” approach. With this technology, the porogens are built into a dielectric film and are degassed during the post-treatment, leaving pores in the film. Applied Materials (Black Diamond IIx; III), Novellus systems (ELK Coral), Trikon (Orion), and ASM are amongst the companies working on this approach. Suppliers of spin-on porous dielectric materials include Dow Chemicals (SiLK), Rohm & Haas (Zirkon), and JSR.
However, it is known in the art that a silicon oxide-containing material (like a carbonated silicon dioxide) has a substantial population of surface hydroxyl (silanol) groups on its surface. These groups have a strong tendency to take up water because they are highly polarized. They are generated by the break up of four and six member bulk siloxane (Si—O—Si) bridges at the surface of the material. These siloxane structures at the material surface have an uncompensated electric potential and so can be considered to be “strained”. They react readily with ambient moisture to form the surface hydroxyl groups. If the silicon oxide-containing material is porous, the surface hydroxyls and the adsorbed water molecules tend to propagate into the bulk of the material, causing an increase in the dielectric constant and reducing film reliability.
A comparable effect occurs in other materials, such as metal oxides, present on the surface of a wafer. The metal ion-oxide bonds located at the surface of the material have an uncompensated electric potential. This likewise leads to a ready reaction with ambient moisture so as to form surface hydroxyl groups. Once again, if the material is porous, the surface hydroxyls and adsorbed water molecules will propagate to the bulk of the material and lead to an unwanted increase in dielectric constant.
As mentioned above, carbonated silicon oxide is often used as a porous dielectric material. Its carbon-rich surface has relatively fewer strained oxide bonds. Thus, there is a reduced population of surface hydroxyls at the surface of the material.
However, the tendency for water uptake is still quite high in carbon-containing porous dielectric materials after a dry etch process. The oxidizing plasma reduces the carbon content at the surface of the material and therefore increases the population of surface hydroxyls. The dielectric constant k therefore increases after dry etching, so the k value of the film must be “restored.” An example of such a restoration of the dielectric constant is the application of a supercritical CO2 treatment with hexamethyldisilazane (HMDS).
In addition to problems caused by moisture present in ambient air, it is also conventional to use aqueous cleaning solutions to clean the surface of the wafer during semiconductor fabrication.
For example, when a semiconductor integrated circuit is manufactured, vias and other trench-like structures must be etched in one or more layers formed on a semiconductor substrate. When vias or trench-like structures are etched, polymer residues may build up in the via/trench because of a reaction between hydrocarbon etchant gases in the plasma and the substrate material. In addition, metallic species (e.g. copper) may be inadvertently sputtered onto the sidewalls.
It is thus desirable to clean a surface of the wafer to remove the polymer residues (and metallic species, if any), before proceeding to the subsequent stages in the manufacturing process. Conventional cleaning processes may use aqueous cleaning solutions such as dilute hydrofluoric acid (HF) or organic acid/base solutions.
However, these types of aqueous cleaning solutions are not suitable when the surface being cleaned has a tendency to adsorb water, and particularly when the surface is porous, such as the surface of a porous dielectric layer. If aqueous cleaning solutions were used after via etching to clean a wafer having a porous dielectric layer thereon, the porous material adsorbs water from the cleaning fluids. This problem may be even more problematic if the dielectric layer is damaged by plasma etching during the etching process.
Besides negatively affecting the dielectric constant of the porous dielectric layer, adsorbed water can also cause problems during subsequent stages in the manufacture of the circuit, notably degassing and reliability problems.
For the reasons described above, it is important to prevent water adsorption and uptake if porous dielectric materials are used to form interconnects. Moreover, moisture uptake in a porous dielectric could possibly corrode tantalum-based barrier layers.
Some known approaches to combat moisture uptake by porous dielectric materials during manufacture and use of a semiconductor integrated circuit include “dielectric restoration” as referred to hereinabove, as well as “pore sealing.”
Pore sealing involves prevention of access to the pores in the porous material, for example, by modifying the surface of the porous material (e.g. using an organosilane treatment), or by depositing a thin dielectric film on the surface of the porous dielectric layer.
The latter solution of depositing a thin dielectric film has a disadvantage of increasing the k value of the layer. In some cases, it is applied to the porous dielectric layer after vias have been etched therein.
Accordingly, an alternative known approach for post-via-etch cleaning of a wafer having a porous dielectric material involves applying supercritical carbon dioxide (CO2) to the etched surface as mentioned above. However, this approach disadvantageously requires investment in new process equipment which is at a more experimental stage in development than the cleaning equipment commonly used in the semiconductor manufacturing industry.
In addition to the foregoing issues concerning porous dielectric materials, subsequent conventional metallization (i.e., the formation of various metal layer structures) is relatively slow and complex, and is therefore relatively expensive. In this regard, atomic layer deposition, chemical vapor deposition, and physical vapor deposition are typical methods for forming metal layers. Such processes require, in particular, separate and relatively complex process equipment operating under strict operating conditions.